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CY7C53120L8 CY7C53150L
3.3V Neuron(R) Chip Network Processor
Features
* 3.3V operation * Three 8-bit pipelined processors for concurrent processing of application code and network traffic * Hardware UART/SPI interface * Eleven-pin I/O port programmable in 38 modes for fast application program development. I/O port is 5V input tolerant * Two 16-bit timer/counters for measuring and generating I/O device waveforms * Five-pin communication port that supports direct connect and network transceiver interfaces, and operates at 3.3V or 5V * Programmable pull-ups on IO4-IO7 and 20-mA sink current on IO0-IO3 * Unique 48-bit Neuron ID number in every device to facilitate network installation and management * 0.35-m Flash process technology * On-chip LVD circuit with programmable trip point and digital filter settings * Programmable Pulse Stretching reset * 4,096 bytes of SRAM for buffering network data, system, and application data storage * 2.75 KBytes (CY7C53150L), 8KBytes (CY7C53120L8) of Flash memory with on-chip charge pump for flexible storage of configuration data and application code * Addresses up to 56 KBytes of external memory (CY7C53150L) * 16 KBytes (CY7C53120L8) of ROM containing LonTalk network protocol firmware * Maximum input clock operation of 20MHz over -40C to 85C[1] temperature range * 64-pin TQFP package (CY7C53150L) * 32-pin SOIC or 44-pin TQFP package (CY7C53120L8) Logic Block Diagram
Media Access Control Processor Network Processor Application Processor 4KBytes RAM Flash ROM (CY7C53120L8) Internal Data Bus (0:7) Internal Address Bus (0:15)
Functional Description
The 3.3V Neuron chip (CY7C53120L8/3150L) is a low-power version of the 5V Neuron chip with a number of feature enhancements. The CY7C53120L8/3150L Neuron chip implements a device for LonWorks distributed intelligent control networks. It incorporates, on a single chip, the necessary communication and control functions, both in hardware and firmware, that facilitate the design of a LonWorks device. The CY7C53120L8/3150L supports all the functionality of the 5V CY7C531x0 Neuron chip. Additionally it features 4KBytes of RAM, 8KBytes of Flash memory (CY7C53120L8), and hardware UART/SPI. The CY7C53120L8/3150L has an 11-pin configurable I/O block. The I/Os are all 5V-tolerant to allow interfacing to TTL Compatible 5V components and microcontrollers. The CY7C53120L8/3150L contains a very flexible five-pin communication port that can be configured to interface with a wide variety of media transceivers at a wide range of data rates. The communication port can operate at either 3.3V or 5V. In 5V mode the communication port is completely backward compatible with existing 5V transceivers. The most common transceiver types are twisted-pair, powerline, RF, IR, fiber-optics, and coaxial. The CY7C53150L incorporates an external memory interface that can address up to 56KBytes with 8KBytes of the address space mapped internally. LonWorks devices that require large application programs can take advantage of this external memory capability. Services at every layer of the OSI networking reference model are implemented in the LonTalk firmware-based protocol stored in 16KBytes ROM (CY7C53120L8), or off-chip memory (CY7C53150L). The firmware also contains 38 preprogrammed I/O drivers, simplifying application programming. The application program is stored in the Flash memory (CY7C53120L8) and/or off-chip memory (CY7C53150L), and may be updated by downloading over the network.
Communications Port Two Timer/Counters 4-pin UART/SPI I/O Block Oscillator, Clock, and Control CLK1 CLK2 SERVICE RESET IO10 : IO7 IO6 : IO0 CP4 CP0
External Address and Data Bus (CY7C53150L)
Note: 1. Maximum junction temperature is 105C. TJunction = TAmbient + V*I*JA. 32-pin SOIC JA = 61.07C/W. 44-pin TQFP JA = 69.5C/W. 64-pin TQFP JA = 56.15C/W.
Cypress Semiconductor Corporation Document #: 38-10002 Rev. *E
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised November 2, 2004
CY7C53120L8 CY7C53150L
Pin Configurations
CY7C53150L 64-lead Thin Quad Flat Pack
NC[2] A15 E R/W VDD D0 D1 VDD VDD VSS D2 D3 D4 D5 D6 D7
NC[2] A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 CY7C53150L-64AI 23 58 22 59 21 60 20 61 19 62 18 63 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CP4 CP3 CP2 CP1 CP0 NC[2] CVDD VSS CLK1 CLK2 VDD VSS VDD VSS NC[2] SERVICE
Vss Vpp IO4 IO5 IO6 SS/IO7 SCLK/RXD/IO8 MISO/IO9
Notes: 2. No Connect (NC) -- should not be used. (These pins may be used for internal testing.) 3. The smaller dimple at the bottom left of the marking indicates pin 1.
Document #: 38-10002 Rev. *E
MOSI/TXD/IO10
IO0 IO1
IO2 IO3 RESET VDD
NC[2]
Pin 1 Indicator [3]
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CY7C53120L8 CY7C53150L
Pin Configurations (continued)
44-lead TQFP IO10/MOSI/TXD IO8/SCLK/RXD
IO9/MISO
IO7/SS
NC[2]
NC[2]
32-lead SOIC RESET VDD IO4 IO3 IO2 IO1 IO0 SERVICE VSS Vpp VDD VDD VSS CLK2 CLK1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD VSS NC[2] IO5 IO6 IO6 IO7/SS IO5 IO8/SCLK/RXD VSS IO9/MISO VDD VDD NC[2] IO10/MOSI/TXD RESET VSS VDD CP4 CP3 IO4 CP1 IO3 CP0 NC[2] CVDD CP2 PIN 1 INDICATOR 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 CY7C53120L8-44AI 22 21 20 19 18 17 16 15 14 13 12 NC[2] CP1 CP0 CVDD CP2 NC[2] VSS CLK1 CLK2 VSS NC[2]
CY7C53120L8-32SI
NC[2]
NC[2]
SERVICE
Pin Definitions
Pin Name CLK1 CLK2 Output I/O Pin Function Oscillator connection. Leave open when external clock is input to CLK1. Maximum of one external load. Reset pin (active LOW). Note. The allowable external capacitance connected to the RESET pin is 100-1000 pF. Service pin (active LOW). Alternates between input and output at a 76-Hz rate. Large current-sink capacity (20mA). General I/O port. The output of timer/ counter 1 may be routed to IO0. The output of timer/counter 2 may be routed to IO1. CY7C53150L CY7C53120L8 CY7C53120L TQFP-64 SOIC-32 8 TQFP-44 Pin No. Pin No. Pin No. 24 23 15 14 15 14
Input (5V tolerant) Oscillator connection or external clock input.
RESET
I/O (Built-In Pull-up) I/O (Built-In Configurable Pull-up) I/O
6
1
NC[2]
IO2
IO1
IO0
VSS
Vpp
VDD
VDD
NC[2]
CP4
CP3
VDD
VSS
40
SERVICE
17
8
5
IO0-IO3
2, 3, 4, 5
7, 6, 5, 4
4, 3, 2, 43
IO4-IO7
I/O (Built-In Configurable Pull-ups) I/O Input
General I/O port. The input to timer/counter 1 10, 11, 12, 13 may be derived from one of IO4-IO7. The input to timer/counter 2 may be derived from IO4. General I/O port. May be used for serial communication under firmware control. Slave Select. Muxed with IO7. 14, 15, 16 13
3, 30, 29, 28
42, 36, 35, 32
IO8-IO10 SS
27, 26, 24 28
31, 30, 27 32 Page 3 of 14
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CY7C53120L8 CY7C53150L
Pin Definitions (continued)
Pin Name SCLK/RXD I/O MISO MOSI/TXD I/O I/O I/O Pin Function SPI Clock or UART RXD. Muxed with IO8. Can be configured as Open Drain Output. SPI Master In/Slave Out (MISO) Muxed with IO9. Can be configured as Open Drain Output. SPI Master out/Slave In (MOSI) or UART TXD. Muxed with IO10. Can be configured as Open Drain Output. Bidirectional memory data bus. Read/write control output for external memory. Enable clock control output for external memory. Memory address output port. CY7C53150L CY7C53120L8 CY7C53120L TQFP-64 SOIC-32 8 TQFP-44 Pin No. Pin No. Pin No. 14 15 16 27 26 24 31 30 27
D0-D7 R/W E A0-A15
I/O Output Output Output
43, 42, 38, 37, 36, 35, 34, 33 45 46 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 47 7, 20, 22, 40, 41, 44 8,19, 21, 25, 39 26 9
N/A N/A N/A N/A
N/A N/A N/A N/A
VDD VSS CVDD [4] VPP CP0-CP4 NC
Input Input Input Input
Power input (3.3V nom.). All VDD pins must be connected together externally. Power input (0V, GND). All VSS pins must be connected together externally. Power input, 5V or 3.3V depending on Communications Port Voltage. In-circuit test mode control. If VPP is high when RESET is asserted, the I/O, address and data buses become Hi-Z.
2, 11, 12, 25, 32 9, 13, 16, 23, 31 18 10
9, 10, 29, 38, 41 7,13, 16, 26, 37 19 8
Communication Bidirectional port supporting communicaNetwork Interface tions in three modes. -
28, 29, 30, 31, 19, 20, 17, 21, 20, 21, 18, 24, 32 22 25 - 1, 6, 11, 12, 17, 22, 23, 28, 33, 34, 39, 44
No connect. Must not be connected on the 1, 18, 27, 48, user's PC board, since they may be connected 49 internal to the chip.
Memory Usage
All Neuron chips require system firmware to be present when they are powered up. In the case of the CY7C53120L8, this firmware is preprogrammed in the factory in an on-chip ROM. In the case of the CY7C53150L, the system firmware must be present in the first 16KBytes of an off-chip nonvolatile memory such as Flash, EPROM, EEPROM, or NVRAM. Because the system firmware implements the network protocol, it cannot itself be downloaded over the network. For the CY7C53120L8, the user application program is stored in on-chip Flash memory. It may be programmed using a device programmer before board assembly, or may be programmed in-circuit after board assembly through a proprietary 11-pin programming interface or over the LonTalk network from an external network management tool. For the CY7C53150L, the user application program is stored in on-chip Flash Memory and also in off-chip memory. The
user program may initially be programmed into the off-chip memory device using a device programmer.
Flash Memory Retention and Endurance
Data and code stored in Flash Memory is guaranteed to be retained for at least ten years for programming temperature range of -40C to 85C. The Flash memory can typically be written 100,000 times without any data loss[5]. An erase/write cycle takes 20 ms. The system firmware extends the effective endurance of the Flash memory in two ways. If the data being written to a byte of Flash memory is the same as the data already present in that byte, the firmware does not perform the physical write. So for example, an application that sets its own address in Flash memory after every reset will not use up any write cycles if the address has not changed. In addition, system firmware version 15 or higher is
Notes: 4. Power supply sequencing is required. Power must be applied such that, VDD (3.3V) supply must not trail CVDD (3.3V/5V) supply on power-up by more than 1V until VDD reaches its normal operating voltage. Ramps can be simultaneous as long as the above condition is maintained. 5. For detailed information about data retention after 100K cycles, please see Cypress qualification report.
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able to aggregate writes to eight successive address locations into a single write for CY7C53120L8 devices. For example, if 8KBytes of code is downloaded over the network, the firmware would execute only 1024 writes rather than 8,192.
Hardware Serial Communication Engine
The CY7C53120L8/3150L features a hardware Serial Communication Engine. The hardware engine is capable of performing high-speed communications in either SPI or UART mode. Serial Peripheral Interface (SPI) Mode SPI mode is 4-pin synchronous serial communications interface that can be set as either a Master or a Slave[6]. SPI Pin IO7 IO8 IO9 IO10 Description Slave Select (SS) Hardware SPI Serial Clock (SPSCK) Master Input/Slave Output (MISO) Master Output/Slave Input (MOSI)
Manufacturer ID
The manufacturer ID is 0x02 for both the CY7C53150L and CY7C53120L8. The major model ID is 0x02 for the CY7C53150L and 0x10 for the CY7C53120L8. The minor model ID is 0x08 for both ICs.
Low-Voltage Inhibit (LVI) Operation
The on-chip Low-voltage Inhibit circuit trips the Neuron chip reset circuit whenever the VDD input drops below a set value. The default value of the LVI trip point is 2.77V, with a variation of 100mV across process and temperature. Every time power is reapplied to the chip, the LVI trip point gets set to this default value. Through the application code, the trip point can be programmed to be one of 16 points between 2.77V and 3.19V. The purpose of the LVI circuit is to prevent the corruption of nonvolatile memory during voltage drops. A lower value of trip point voltage decreases the likelihood of the LVI tripping due to noise on VDD. A lower setting is therefore recommended for circuits with a lot of noise on the power supply. In circuits that do not have excessive noise it is recommended that the LVI trip point be increased which results in better flash protection in case of real power loss scenarios. Internal circuitry is provided to ensure that in a power loss scenario, writes to non-volatile memory that have already started get completed. To ensure proper functioning of this circuitry, the VDD droop time (during power down or power loss) should be at least 10ms from the time LVI circuit trips and voltage reaches 2.77V. The LVI also features a programmable digital filter used to filter out VDD noise. This is another method of decreasing the possibility of the LVI being triggered by the noise as opposed to true power loss events. The digital filter is programmable to a value between 16 and 128 clock cycles. The value chosen depends on the frequency of the VDD noise where the digital filter period should slightly exceed the minimum frequency noise seen on VDD. The LVI digital filter defaults to 128 clock cycles.
SPI communication is a point-to-point or point-to-multi-point interface that can be configured as master/slave, singlemaster/multiple-slaves or multiple-masters/single-slave. The master initiates all communication between slave and master. The master drives the SPSCK signal, which is a clock used to synchronize all data communication between master and slave. Slave Select (SS) is an input to the Neuron chip in both the Master and the Slave modes. In Slave mode, SS is active low with the Slave communicating only when SS is low. In Master mode, the SPI engine functions only when the SS signal is held high. SS can be hard wired high or low or it can be wired to signals being generated from other sources. The Neuron Chip can use IO0 through IO6 for selecting between multiple slaves when acting as a master. MOSI and MISO are used to send and receive data over SPI. MOSI is a data output in Master mode and is an input in Slave mode. MISO is an input in Master mode and is an output in Slave mode. The phase and polarity of the data relative to the clock signal is programmable and can be configured in four possible modes. The SPI interface can communicate at a maximum of 5Mbps data rate with a 20-MHz input clock frequency. The maximum data rate scales with frequency. The data rate is programmable and can be scaled by selecting the desired divisor ranging from 2 to 256 in multiples of 2.
Reset Stretching
At Power-on, the CY7C53120L8/3150L provides internal Reset Stretching of 25ms at 20MHz clock frequency. Power-on Reset Stretch time scales with frequency. After Power-on, Reset Stretch is 50ms independent of frequency of operation. At Power-on the CY7C53120L8/3150L defaults to Reset Stretch enabled. The Reset Stretch can either be left enabled or disabled through software. Reset Stretching eliminates the need for an external pulse stretching LVI which is required when using the CY7C53150 with an external Flash memory.
Serial Communication Interface (UART) Mode
UART mode provides a full-duplex asynchronous NRZ format serial interface for communicating with other devices with either an UART or UART interface. The UART interface is optimized to provide industry standard UART baud rates from the CY7C53120L8/3150L crystal clock rates. UART Pin IO8 IO10 Description Receive Data (RXD) Transmit Data (TXD)
5V-Tolerant Reset
RESET is an Input/Output pin. It is a 5V-tolerant input pin. It can provide 5V-compatible levels when output if an external resistor is connected between pin and 5V supply.
Note: 6. Please see document Errata for CY7C53150L and CY7C53120L8 - 3.3V Neuron Chip (38-17019) for details.
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CY7C53120L8 CY7C53150L
RXD is used to receive serial data at the specified baud rate. TXD is used to transmit data serially at the specified baud rate. The idle state of the TXD and RXD lines is high. All data bytes begin with a start bit which is a `0'; this is followed by eight or nine bits of data, LSB first, and end with a stop bit which is a return to the idle state of `1.' The number of bits transmitted or received is programmable between eight or nine bits. The ninth bit can be used as a parity bit or as a second stop bit. The maximum baud rate for the UART engine is 921.6 Kbaud with 20-MHz input clock frequency and scales with frequency. The UART can be programmed to run at most of the standard UART baud rates. Programmable Hysteresis Values (3.3V) (Expressed as differential peak-to-peak voltages in terms of VDD) Hysteresis[7] 0 1 2 3 4 5 6 7 Vhys Min. 0.019 VDD 0.038 VDD 0.057 VDD 0.076 VDD 0.095 VDD 0.114 VDD 0.133 VDD 0.152 VDD Vhys Typ. 0.027 VDD 0.054 VDD 0.081 VDD 0.108 VDD 0.135 VDD 0.162 VDD 0.189 VDD 0.216 VDD Vhys Max. 0.035 VDD 0.070 VDD 0.105 VDD 0.140 VDD 0.175 VDD 0.210 VDD 0.245 VDD 0.280 VDD
Communications Port
The Neuron chip includes a versatile 5-pin communications port that can be configured in three different ways. The Communications port can operate at either 3.3V or 5V. The Communication port can be made backward-compatible with existing 5V transceivers by supplying a 5V supply to the CVDD pin. In Single-ended Mode, pin CP0 is used for receiving serial data, pin CP1 for transmitting serial data, and pin CP2 enables an external transceiver. Data is communicated using Differential Manchester encoding. In Special Purpose Mode, pin CP0 is used for receiving serial data, pin CP1 for transmitting serial data, pin CP2 transmits a bit clock, and pin CP4 transmits a frame clock for use by an external intelligent transceiver. In this mode, the external transceiver is responsible for encoding and decoding the data stream. In Differential Mode, pins CP0 and CP1 form a differential receiver with built-in programmable hysteresis and low-pass filtering. Pins CP2 and CP3 form a differential driver. Serial data is communicated using Differential Manchester encoding. The following tables describe the communications port when used in Differential Mode.
Programmable Hysteresis Values (5V) (Expressed as differential peak-to-peak voltages in terms of VDD) Hysteresis[7] 0 1 2 3 4 5 6 7 Vhys Min. 0.019 VDD 0.040 VDD 0.061 VDD 0.081 VDD 0.101 VDD 0.121 VDD 0.142 VDD 0.162 VDD Vhys Typ. 0.027 VDD 0.054 VDD 0.081 VDD 0.108 VDD 0.135 VDD 0.162 VDD 0.189 VDD 0.216 VDD Vhys Max. 0.035 VDD 0.068 VDD 0.101 VDD 0.135 VDD 0.169 VDD 0.203 VDD 0.236 VDD 0.270 VDD
Programmable Glitch Filter Values[8](Receiver (end-to-end) filter values expressed as transient pulse suppression times) Filter (F) 0 1 2 3 Min. 10 120 240 480 Typ. 75 410 800 1500 Max. 140 700 1350 2600 Unit ns ns ns ns
Operating the Communications Port at 5V
The 3.3V Neuron device has a 5V compatible communications port. In order to operate the Communications port at 5V, CVDD has to be supplied with 5V. In this case CLK2 output will still be at 3.3V but a buffered copy of CLK2 can be obtained on CP3 pin of the communications port. When the comm port is in Single-ended Mode and the CVDD is at 5V, there will be a buffered 5V version of CLK2 and the CP3 pin.
Receiver[9] (End-to-End) Absolute Asymmetry (Worst-case across hysteresis) Filter (F) 0 1 2 3 Max (tPLH - tPHL) 35 150 250 400 Max (tPLH - tPHL) 24 Unit ns ns ns ns
CP0 - CP1
Vhys + 200 mV CP0 VDD/2 CP1
Differential Receiver (End-to-End) Absolute Symmetry[10, 11] Filter (F) Hysteresis (H) 0 0 Unit ns
3 ns
Figure 1. Receiver Input Waveform
Notes: 7. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value. 8. The maximum data rate for the differential transceiver is 1.25 Mbps. 9. Receiver input, VD = VCP0 - VCP1, at least 200 mV greater than hysteresis levels. See Figure 1. 10. CP0 and CP1 inputs each 0.60 Vp - p, 1.25 MHz sine wave 180 out of phase with each other as shown in Figure 8 VDD = 5V, Figure 9 VDD = 3.3V. 11. tPLH: Time from input switching states from low to high to output switching states. tPHL: Time from input switching states from high to low to output switching states.
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CY7C53120L8 CY7C53150L
Electrical Characteristics (VDD = 3.0V-3.6V)
Parameter VDD CVDD (5V) VIL VIH VOL Power Supply Voltage Power Supply Voltage Input Low Voltage IO0-IO10, CP0, CP3, CP4, SERVICE, D0-D7, RESET CP0, CP1 (Differential) Input High Voltage IO0-IO10, CP0, CP3, CP4, SERVICE, D0-D7,RESET CP0, CP1 (Differential) Low-Level Output Voltage Iout < 20 A Standard Outputs (IOL = 1.4mA)[12] High Sink (IO0-IO3), SERVICE, RESET (IOL = 20mA) High Sink (IO0-IO3), SERVICE, RESET (IOL = 10mA) Maximum Sink (CP2, CP3) (IOL = 40mA) Maximum Sink (CP2, CP3) (IOL = 15mA) High-Level Output Voltage Iout < 20 A Standard Outputs (IOH = -1.4mA)[12] High Sink (IO0 - IO3), SERVICE (IOH = -1.4mA) Maximum Source (CP2, CP3) (IOH = -40mA) Maximum Source (CP2, CP3) (IOH = -15mA) Hysteresis (Excluding CLK1) Input Current (Excluding Pull-Ups) (VSS to VDD)[13] Pull-Up Source Current (Vout = 0 V, Output = Operating Mode Supply Current[14] 20-MHz Clock 10-MHz Clock 5-MHz Clock 2.5-MHz Clock 1.25-MHz Clock 0.625-MHz Clock[15] Sleep Mode Supply Current[14] High-Z)[13] CVDD(3.3V) Power Supply Voltage Description Min. 3.0 3.0 4.75 -- -- 2.0 Programmable -- -- -- -- -- -- VDD - 0.1 VDD - 0.4 VDD - 0.4 VDD - 1.0 VDD - 0.4 175 -- 60 -- -- -- -- -- -- -- Typ. 3.3 3.3 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6 Max. 3.6 3.6 5.25 0.8 Programmable -- -- 0.1 0.4 0.8 0.4 1.0 0.4 -- -- -- -- -- -- 10 260 21 13 8 5 3.3 2 10 Unit V V V V
V
V
VOH
V
Vhys Iin Ipu IDD
mV A A mA
IDDsleep
A
LVI Trip Point (VDD)
Part Number CY7C53120L8, and CY7C53150L Unit Programmable between 2.77V and 3.19V
Notes: 12. Standard outputs are IO4-IO10, CP0, CP1, and CP4. (RESET is an open drain input/output. CLK2 must have < 15 pF load.) For CY7C53150L, standard outputs also include A0-A15, D0-D7, E, and R/W. 13. IO4-IO7 and SERVICE have configurable pull-ups. RESET has a permanent pull-up. 14. Supply current measurement conditions: VDD = 3.3V, all outputs under no-load conditions, all inputs < 0.2V or > (VDD - 0.2V), configurable pull-ups off, crystal oscillator clock input, differential receiver disabled. The differential receiver adds approximately 200 A typical and 600 A maximum (at 5V) when enabled. It is enabled on either of the following conditions: * Neuron Chip in Operating mode and Comm Port in Differential mode. * Neuron Chip in Sleep mode and Comm Port in Differential mode and Comm Port Wake-up not masked. 15. Supported through an external oscillator only.
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CY7C53120L8 CY7C53150L
External Memory Interface Timing -- CY7C53150L, VDD 10% (VDD = 3.0V to 3.6 V, TA = -40C to+ 85C[1])
Parameter tcyc PWEH PWEL tAD tAH tRD tRH tWR tWH tDSR tDHR tDHW tDDW tDHZ tDDZ tacc Pulse Width, E High[17] Pulse Width, E Low[17] Delay, E High to Address Valid Address Hold Time After E High Delay, E High to R/W Valid Read R/W Hold Time Read After E High Delay, E High to R/W Valid Write R/W Hold Time Write After E High Read Data Setup Time to E High Data Hold Time Read After E High Data Hold Time Write After E High[18, 19] Delay, E Low to Data Valid Data Three State Hold Time After E Low[20] Delay, E High to Data Three-State[19] External Memory Access Time (tacc = tcyc - tAD - tDSR) at 20-MHz input clock Description Memory Cycle Time (System Clock Period)
[16]
Min. 100 tcyc/2 - 5 tcyc/2 - 5 -- 10 -- 5 -- 5 15 0 10 -- 0 -- 50
Max. 3200 tcyc/2 + 5 tcyc/2 + 5 35 -- 25 -- 25 -- -- -- -- 12 -- 42 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Differential Transceiver Electrical Characteristics
Characteristic at 3.3V Receiver Common Mode Voltage Range to maintain Input Offset Voltage Propagation Delay (F = 0, VID = Vhys/2 + 200 mV) Input Resistance Wake-up Time Differential Output Impedance for CP2 and CP3[22] Min.
[21]
Min. hysteresis[21] 0.6 0.4 -0.05Vhys - 35 -- 5 --
Max. VDD - 1.5 VDD - 1.3 0.05Vhys + 35 230 ns -- 10 35 Max. VDD - 2.2 VDD - 1.75 0.05Vhys + 35 230 ns -- 10 35
Unit V V mV ns M s Unit V V mV ns M s
Receiver Common Mode Range to operate with unspecified hysteresis
Characteristic at 5V Receiver Common Mode Voltage Range to maintain hysteresis Input Offset Voltage Propagation Delay (F = 0, VID = Vhys/2 + 200 mV) Input Resistance Wake-up Time Differential Output Impedance for CP2 and CP3[22] Receiver Common Mode Range to operate with unspecified hysteresis
1.2 0.9 -0.05Vhys - 35 -- 5 --
Notes: 16. tcyc = 2(1/f), where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz). 17. Refer to Figure 3 for detailed measurement information. 18. The data hold parameter, tDHW, is measured to the disable levels shown in Figure 4, rather than to the traditional data invalid levels. 19. Refer to Figure 5 and Figure 4 for detailed measurement information. 20. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information. 21. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs. 22. Z0 = {Sum of DC drop across CP2 and CP3 pads @40mA current} / 40mA for CVdd +/-5%.
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CY7C53120L8 CY7C53150L
TEST SIGNAL
CL = 20 pF for E CL CL = 30 pF for A0-A15, D0-D7, and R/W CL = 50 pF for all other signals
Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified
PWEH 2.0V 0.8V
PWEL 2.0V
Figure 3. Test Point Levels for E Pulse Width Measurements
DRIVE TO 2.4V DRIVE TO 0.4V
2.0V 0.8V A B 2.0V 0.8V
A -- Signal valid-to-signal valid specification (maximum or minimum) B -- Signal valid-to-signal invalid specification (maximum or minimum)
Figure 4. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified
VOH - 0.5 V
VOL + 0.5 V VOH - Measured high output drive level VOL - Measured low output drive level
Figure 5. Test Point Levels for Driven-to-Three-State Time Measurements
TEST SIGNAL CL = 30 pF
VDD/2 ILOAD = 1.4mA
Figure 6. Signal Loading for Driven-to-Three-State Time Measurements
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CY7C53120L8 CY7C53150L
tcyc E 20 pF Load PWEH PWEL
Address (A0 - A15) 30 pF Load
tAD Address
tAD Address tAH
tAD Address tAH tWR
tAD Address tAH tAH
tRD R/W 30 pF Load tRH tDSR Data In tDHR tDHR
tWH
tDSR Data (In) (D0 - D7) Data In
tDDW tDHZ tDHW
tDDZ
tDDW
tDDZ tDHZ tDHW Data Out
Data (Out) (D0 - D7) 30 pF Load
Data Out
Memory READ
Memory READ
Memory WRITE
Memory WRITE
Figure 7. External Memory Interface Timing Diagram
Document #: 38-10002 Rev. *E
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CY7C53120L8 CY7C53150L
Voltage
4 3 2
V(CP0)
Time
Vcm
V(CP1) Voltage V(CP0)-V(CP1)
1
Vh
-1
Vtrip+
Time Vtrip-
Neuron 5V Chip's Internal 0V Comparator Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2 Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 8. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 5V Operation
Voltage
3
V(CP0)
Time
Vcm
2 1
V(CP1) Voltage
0.5
V(CP0)-V(CP1) Vtrip+ Time Vtrip-
Vh
-0.5
Neuron 3.3V Chip's Internal 0V Comparator Common-Mode voltage: Vcm = ( V(CP0) + V(CP1) ) / 2 Hysteresis Voltage: Vh = [Vtrip+] - [Vtrip-]
Figure 9. Differential Receiver Input Hysteresis Voltage Measurement Waveforms for 3.3V Operation
Document #: 38-10002 Rev. *E
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CY7C53120L8 CY7C53150L
Ordering Information
Part Number CY7C53150L-64AI CY7C53120L8-32SI CY7C53120L8-44AI Flash (KBytes) 2.75 8 8 ROM (KBytes) 0 16 16 SRAM (KBytes) 4 4 4 Max. Input Clock (MHz) 10 20 20 Package Name A65 S34 A44 Package Type 64-lead Thin Plastic Quad Flat Pack 32-lead (450 mil) Molded SOIC 44-lead Thin Plastic Quad Flat Pack
Package Diagrams
64-lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-*B
Document #: 38-10002 Rev. *E
Page 12 of 14
CY7C53120L8 CY7C53150L
Package Diagrams (continued)
44-lead Thin Plastic Quad Flat Pack A44
51-85064-*B
32-Lead (450 MIL) Molded SOIC S34
16 1
0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430]
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600]
0.101[2.565] 0.111[2.819]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508]
0.023[0.584] 0.039[0.990]
51-85081-*B
SEATING PLANE
Echelon, LonWorks, LonTalk, and Neuron are registered trademarks of Echelon Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-10002 Rev. *E Page 13 of 14
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C53120L8 CY7C53150L
Document History Page
Document Title: CY7C53150L/CY7C53120L8 3.3V Neuron(R) Chip Network Processor Document Number: 38-10002 REV. ** *A ECN NO. 121963 123762 Issue Date 12/12/02 03/03/03 Orig. of Change PVO PVO New data sheet Changed Advance Information to Preliminary Added information on LVI, UART/SPI, Reset Stretching Corrected values of ROM, Hysteresis, and IPU Added 100-pin TQFP pin definitions Made minor corrections to grammar and formatting Add information on Power Sequence Corrected values of ROM Added default values of LVI, LVI filter and SPI divisor. Corrected Ipu Current limit values Clarified Reset Stretch times Corrected pin definitions (pins 10 to 14) on 100pin TQFP diagram Added Theta-JA value for the 100-pin TQFP package Changed part numbers to CY7C53120L8 / CY7C53150L Added ordering information table Add footnote #4 on Power supply considerations Corrected Theta-JA values for all packages Added information on LVI limitations Added information on Reset operation at 5V Added information on Communication Port operation at 5V Added information on Manufacturer ID Removed 100-pin package Added SPI Slave Mode Errata Note Description of Change
*B
125311
03/21/03
KBO
*C
130922
12/31/03
TGE
*D *E
210068 283876
See ECN See ECN
TGE TGE
Document #: 38-10002 Rev. *E
Page 14 of 14

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